PXD10RM Datasheet, PDF (403/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Table 12-48. Soft Lock HSYNC/VSYNC PARA Register Field Descriptions (continued)
Field
4
SLB_HSYNC
5
SLB_VSYNC
Description
Soft Lock Bit for HSYNC Register.
1’b1: Associated protected register is locked for write access
1’b0: Associated protected register is not locked & writeable
Soft Lock Bit for VSYNC Register.
1’b1: Associated protected register is locked for write access
1’b0: Associated protected register is not locked & writeable
12.3.4.44 Soft Lock POL Register
Figure 12-54 represents the Soft Lock POL Register.
Offset: 0x314
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R0 0 0 0
00000000000
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 51.
Figure 12-54. Soft Lock POL Register
Field
0
WEN_POL
4
SLB_POL
Table 12-49. Soft Lock POL Register Field Descriptions
Description
Write Enable for Soft Lock Bit SLB_POL
1’b1: Value is written to SLB
1’b0: SLB is not modified
Soft Lock Bit for SYN_POL Register.
1’b1: Associated protected register is locked for write access
1’b0: Associated protected register is not locked & writeable
12.3.4.45 Soft Lock L0_TRANSP Register
Figure 12-55 represents the Soft Lock L0_TRANSP register.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
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