PXD10RM Datasheet, PDF (1185/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Time of Integration Phase
OFFCNC = 2’b00
OFFCNC = 2’b01
OFFCNC = 2’b10
OFFCNC = 2’b11
0x1FFF
0x1BFF 0x17FF 0x13FF 0x0FFF 0x0BFF 0x07FF
Sample Down Counter for ITGCNTLD = 0x1FFF
Initial polarity setting
Reverted polarity setting
0x03FF
0x0x000
Figure 36-11. Offset Cancellation Polarity Distribution
If the shift process shifts out LS bits from the ITGCNTLD register (non-integer divide) the number shifted
out creates an additional polarity flip which lasts the appropriate number of DCNT update periods.
36.4.2 Stepper Stall Detection Measurement
This part of the functional description deals with the main intended use case of the SSD block, this is the
detection of the scale end boundaries of the gauge pointer moved by the SM which, in turn, is driven by
the SSD block. For details of the related sub blocks refer to Section 36.4.1, Main Building Blocks of the
SSD”.
36.4.2.1 Overview of the SSD Measurement
The generic flow of SSD measurement is given in Figure 36-12 below, the numbers denoted at each step
belong to the detailed explanations given in Section 36.4.2.2, Details of the SSD Measurement”.
The two phases of the BIS are executed in sequence:
1. Blanking phase: Since the non-driven coil used for measurement was driven in the previous step
switching transients are induced when changing from the driven into the non-driven state.
Therefore both pins of the non-driven coil are connected to one of the analog supply voltages
VDDM or VSSM (depending from the RCIR bit) to allow recirculation of these transient currents.
2. Integration phase: This is the actual measurement where the ITGACC register is changed
according to the results of the -modulator of the analog block.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
36-19