PXD10RM Datasheet, PDF (1307/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Table B-2. Detailed register map (continued)
Register Description
SWT Service Register
SWT Counter Output Register
Reserved
Register Name
SWT_SR
SWT_CO
---
STM Section 39.3, Memory map and register definition
Control Register
STM Count Register
Reserved
STM_CR
STM_CNT
-
STM Channel 0 Control Register
STM Channel 0 Interrupt Register
STM Channel 0 Compare Register
Reserved
STM_CCR0
STM_CIR0
STM_CMP0
-
STM Channel 1 Control Register
STM Channel 1 Interrupt Register
STM Channel 1 Compare Register
Reserved
STM_CCR1
STM_CIR1
STM_CMP1
-
STM Channel 2 Control Register
STM Channel 2 Interrupt Register
STM Channel 2 Compare Register
Reserved
STM_CCR2
STM_CIR2
STM_CMP2
-
STM Channel 3 Control Register
STM Channel 3 Interrupt Register
STM Channel 3 Compare Register
Reserved
STM_CCR3
STM_CIR3
STM_CMP3
-
ECSM Section 16.4, Memory map and register description
Processor Core Type
ECSM_PCT
SOC-Defined Platform Revision
ECSM_PLREV
Reserved
-
IPS On-Platform Module Configuration
ECSM_IOPMC
Used
Size
Address
32-bit Base + 0x0010
32-bit Base + 0x0014
--- (Base+0x0018)-
0xFFF3_BFFF
0xFFF3_C000
32-bit Base + 0x0000
32-bit Base + 0x0004
- Base + (0x0008 -
0x000F)
32-bit Base + 0x00010
32-bit Base + 0x00014
32-bit Base + 0x00018
- Base + (0x001C -
0x001F)
32-bit Base + 0x00020
32-bit Base + 0x00024
32-bit Base + 0x00028
- Base + (0x002C -
0x002F)
32-bit Base + 0x00030
32-bit Base + 0x00034
32-bit Base + 0x00038
- Base + (0x003C -
0x003F)
32-bit Base + 0x00040
32-bit Base + 0x00044
32-bit Base + 0x00048
- Base + (0x003C -
0x03FFF)
0xFFF4_0000
16-bit Base + 0x0000
16-bit Base + 0x0002
- Base + (0x0004 -
0x0007)
32-bit Base + 0x0008
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
B-41