PXD10RM Datasheet, PDF (594/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

While UT0.AID is low and UT0.AIE is high, the user may clear AIE, resulting in a Array Integrity Check
abort.
UT0.AID must be checked to know when the aborting command has completed.
Example 17-5. Array Integrity Check of sectors B0F1 and B0F2.
UT0
= 0xF9F99999;
LMS
= 0x00000006;
UT0
= 0x80000002;
do
{ tmp
= UT0;
} while ( !(tmp & 0x00000001) );
data0
= UMISR0;
data1
= UMISR1;
data2
= UMISR2;
data3
= UMISR3;
data4
= UMISR4;
UT0
= 0x00000000;
/* Set UTE in UT0: Enable User Test */
/* Set LSL2-1 in LMS: Select Sectors */
/* Set AIE in UT0: Operation Start */
/* Loop to wait for AID=1 */
/* Read UT0 */
/* Read UMISR0 content*/
/* Read UMISR1 content*/
/* Read UMISR2 content*/
/* Read UMISR3 content*/
/* Read UMISR4 content*/
/* Reset UTE and AIE in UT0: Operation End */
Margin Read
Margin read procedure (either Margin 0 or Margin 1), can be run on unlocked blocks in order to unbalance
the Sense Amplifiers, respect to standard read conditions, so that all the read accesses reduce the margin
vs ‘0’ (UT0.MRV = ‘0’) or vs ‘1’ (UT0.MRV = ‘1’). Locked sectors are ignored by MISR calculation and
ECC flagging. The results of the margin reads can be checked comparing checksum value in UMISR0-4.
Since Margin reads are done at voltages that differ than the normal read voltage, lifetime expectancy of
the Flash macrocell is impacted by the execution of Margin reads.
Doing Margin reads repetitively results in degradation of the Flash Array, and shorten expected lifetime
experienced at normal read levels.
For these reasons the Margin Read usage is allowed only in Factory, while it is forbidden to use it inside
the User Application.
In any case the charge losses detected through the Margin Mode cannot be considered failures of the device
and no Failure Analysis will be opened on them.
The Margin Read Setup operation consists of the following sequence of events:
1. Set UTE in UT0 by writing the related password in UT0.
2. Select the block(s) to be checked by writing 1’s to the appropriate register(s) in LMS or HBS
registers.
Note that Lock and Select are independent. If a block is selected and locked, no Array Integrity
Check will occur.
3. Set eventually UT0.AIS bit for a sequential addressing only.
4. Change the value in the UT0.MRE bit from 0 to 1.
5. Select the Margin level: UT0.MRV=0 for 0’s margin, UT0.MRV=1 for 1’s margin.
6. Write a logic 1 to the UT0.AIE bit to start the Margin Read Setup or skip to step 6 to terminate.
7. Wait until the UT0.AID bit goes high.
17-44
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor