PXD10RM Datasheet, PDF (212/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

8.9.5.1 Control register (CR)
Offset 0x0000
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R₀
0
IDF
ODF
0
NDIV
W
Reset ₀
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R₀
0
0
0
0
0
0
unlock 0 i_lock s_lock
pll_fail 0
en_pll _{mode _once}
pll_fail _{_flag}
_sw
_mask
W
w1c
w1c
Reset ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1 _{Reset value is determined by the SoC integration.}
Table 8-23. Control register (CR)
Table 8-24. CR field descriptions
Field
Description
2-5
The value of this field sets the PLL Input division factor as described in Table 8-25. The reset value
IDF
is set during integration.
6-7
ODF
The value of this field sets the PLL Output division factor as described in Table 8-26. The reset value
is set during integration.
9-15
NDIV
The value of this field sets the PLL Loop division factor as described in Table 8-27. The reset value
is set during integration.
23
en_pll_sw
This bit is used to enable progressive clock switching. After the PLL locks, the PLL output initially is
divided by 8 then progressively divides down until divide by 1.
0 => progressive clock switching disabled
1 => progressive clock switching enabled
Note: The PLL output should not be used if a non-changing clock is needed (such as for serial
communications) until the division has finished
24
mode
This bit is used to activate the 1:1 Mode.
25
This bit is a sticky indication of PLL loss of lock condition. Unlock_once is set when the PLL loses
unlock_once lock. Whenever the PLL reacquires lock, unlock_once remains set. Only a power-on reset can clear
this bit.
27
i_lock
This bit is set by hardware whenever there is a lock/unlock event.It is cleared by software, writing 1.
28
s_lock
This bit is an indication of whether the PLL has acquired lock.
0 => PLL unlocked
1 => PLL locked
8-34
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor