PXD10RM Datasheet, PDF (546/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Table 16-17. RAM Syndrome Mapping for Single-Bit Correctable Errors (continued)
RESR[0:7]
0x38
0x62
0x70
0x60
0x40
0x42
0x44
0x46
0x48
0x4a
0x4c
0x03,0x05........0x4d
> 0x4d
Data Bit in Error
DATA ODD BANK[9]
DATA ODD BANK[8]
DATA ODD BANK[7]
DATA ODD BANK[6]
ECC ODD[6]
DATA ODD BANK[5]
DATA ODD BANK[4]
DATA ODD BANK[3]
DATA ODD BANK[2]
DATA ODD BANK[1]
DATA ODD BANK[0]
Multiple bit error
Multiple bit error
16.4.2.17 RAM ECC Master Number Register (REMR)
The REMR is a 4-bit register for capturing the AXBS bus master number of the last, properly-enabled ECC
event in the RAM memory. Depending on the state of the ECC Configuration Register, an ECC event in
the RAM causes the address, attributes and data associated with the access to be loaded into the REAR,
RESR, REMR, REAT and REDR registers, and the appropriate flag (R1BC or RNCE) in the ECC Status
Register to be asserted.
This register can only be read from the IPS programming model; any attempted write is ignored. See
Figure 16-16 and Table 16-18 for the RAM ECC Master Number Register definition.
Register address: ECSM Base + 0x66
0
1
2
3
4
5
6
7
R
0
0
0
0
REMR[0:3]
W
RESET:
0
0
0
0
x
x
x
x
= Unimplemented
Figure 16-16. RAM ECC Master Number (REMR) Register
Table 16-18. RAM ECC Master Number (REMR) Field Descriptions
Name
4-7
REMR[0:3]
Description
RAM ECC Master Number Register
This 4-bit register contains the AXBS bus master number of the faulting access of the last,
properly-enabled RAM ECC event.
16-20
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor