PXD10RM Datasheet, PDF (486/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Register address: DMA_Offset + 0x0008 (DMAERQH), +0x000c (DMAERQL)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R ERQ ERQ ERQ ERQ ERQ ERQ ERQ ERQ ERQ ERQ ERQ ERQ ERQ ERQ ERQ ERQ
W
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R ERQ ERQ ERQ ERQ ERQ ERQ ERQ ERQ ERQ ERQ ERQ ERQ ERQ ERQ ERQ ERQ
W
47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R ERQ ERQ ERQ ERQ ERQ ERQ ERQ ERQ ERQ ERQ ERQ ERQ ERQ ERQ ERQ ERQ
W
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R ERQ ERQ ERQ ERQ ERQ ERQ ERQ ERQ ERQ ERQ ERQ ERQ ERQ ERQ ERQ ERQ
W
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
= Unimplemented
Figure 15-4. DMA Enable Request (DMAERQH, DMAERQL) Registers
Table 15-4. DMA Enable Request (DMAERQH, DMAERQL) field descriptions
Name
ERQn,
n = 0,... 15
n = 0,... 31
n = 0,... 63
Description
Enable DMA Request n
Value
0 The DMA request signal for channel n is disabled.
1 The DMA request signal for channel n is enabled.
As a given channel completes the processing of its major iteration count, there is a flag in the transfer
control descriptor that may affect the ending state of the DMAERQ bit for that channel. If the TCD.d_req
bit is set, then the corresponding DMAERQ bit is cleared, disabling the DMA request; else if the d_req bit
is cleared, the state of the DMAERQ bit is unaffected.
15.2.1.4 DMA Enable Error Interrupt (DMAEEIH, DMAEEIL)
The DMAEEI{H,L} registers provide a bit map for the implemented channels {16,32,64} to enable the
error interrupt signal for each channel. DMAEEIH supports channels 63-32, while DMAEEIL covers
channels 31-00. The state of any given channel’s error interrupt enable is directly affected by writes to this
register; it is also affected by writes to the DMASEEI and DMACEEI registers. The DMA{S,C}EEI
registers are provided so that the error interrupt enable for a single channel can easily be modified without
the need to perform a read-modify-write sequence to the DMAEEI{H,L} registers.
15-16
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor