PXD10RM Datasheet, PDF (719/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

19.5.2.1 Bypass Mode
When no test operation is required, the BYPASS instruction can be loaded to place the JTAGC into bypass
mode. While in bypass mode, the single-bit bypass shift register is used to provide a minimum-length
serial path to shift data between TDI and TDO.
19.5.2.2 TAP Sharing Mode
There are three selectable auxiliary TAP controllers that share the TAP with the JTAGC. Selectable TAP
controllers include the Nexus port controller (NPC) and PLATFROM. The instructions required to grant
ownership of the TAP to the auxiliary TAP controllers are ACCESS_AUX_TAP_NPC,
ACCESS_AUX_TAP_ONCE, ACCESS_AUX_TAP_TCU. Instruction opcodes for each instruction are
shown in Table 19-3.
When the access instruction for an auxiliary TAP is loaded, control of the JTAG pins is transferred to the
selected TAP controller. Any data input via TDI and TMS is passed to the selected TAP controller, and any
TDO output from the selected TAP controller is sent back to the JTAGC to be output on the pins. The
JTAGC regains control of the JTAG port during the UPDATE-DR state if the PAUSE-DR state was
entered. Auxiliary TAP controllers are held in RUN-TEST/IDLE while they are inactive.
For more information on the TAP controllers refer to Chapter 26, Nexus Development Interface (NDI).
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
19-3