PXD10RM Datasheet, PDF (727/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

19.9 e200z0 OnCE Controller
The e200z0 core OnCE controller supports a complete set of Nexus 1 debug features, as well as providing
access to the Nexus2+ configuration registers. A complete discussion of the e200z0 OnCE debug features
is available in the e200z0 Reference Manual.
19.9.1 e200z0 OnCE Controller Block Diagram
Figure 19-6 is a block diagram of the e200z0 OnCE block.
{ ^From
JTAGC
TCK
e200z0_TRST
e200z0_TMS
Test Access Port (TAP)
Controller
TDO Mux
Control
.
.
TDI
.
.
TAP Instruction Register
(OnCE OCMD)
Bypass Register
External Data Register
e200z0_TDO
(to JTAGC)
.
OnCE Mapped Debug Registers
.
Auxiliary Data Register
Figure 19-6. e200z0 OnCE Block Diagram
19.9.2 e200z0 OnCE Controller Functional Description
The functional description for the e200z0 OnCE controller is the same as for the JTAGC, with the
differences described below.
19.9.2.1 Enabling the TAP Controller
To access the e200z0 OnCE controller, the proper JTAGC instruction needs to be loaded in the JTAGC
instruction register, as discussed in Section 19.5.2.2, TAP Sharing Mode.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
19-11