PXD10RM Datasheet, PDF (270/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

In order to ensure safe working and avoid glitches the following steps must be performed whenever any
updtate in the prescaling rate is desired:
1. Write 0 at both GPREN bit in EMIOSMCR register and UCPREN bit in EMIOSC[n] register, thus
disabling prescalers;
2. Write the desired value for prescaling rate at UCPRE[0:1] bits in EMIOSC[n] register;
3. Enable channel prescaler by writing 1 at UCPREN bit in EMIOSC[n] register;
4. Enable global prescaler by writing 1 at GPREN bit in EMIOSMCR register.
The prescaler is not disabled during either freeze state or negated GTBE input.
9.5.1.4 Effect of Freeze on the Unified Channel
When in debug mode, FRZ bit in the EMIOSMCR register and the FREN bit in the EMIOSC[n] are both
set, the internal counter and Unified Channel capture and compare functions are halted. The UC is frozen
in its current state.
During freeze, all registers are accessible. When the Unified Channel is operating in an output mode, the
force match functions remain available, allowing the software to force the output to the desired level.
Note that for input modes, any input events that may occur while the channel is frozen are ignored.
When exiting debug mode or freeze enable bit is cleared (FRZ in the EMIOSMCR or FREN in the
EMIOSC[n] register) the channel actions resume, but may be inconsistent until channel enters GPIO mode
again.
9.5.2 IP Bus Interface Unit (BIU)
The BIU provides the interface between the Internal Interface Bus (IIB) and the Peripheral Bus, allowing
communication among all submodules and this IP interface.
The BIU allows 8, 16 and 32 bits access. They are performed over a 32-bit data bus in a single cycle clock.
9.5.2.1 Effect of Freeze on the BIU
When the FRZ bit in the EMIOSMCR register is set and the module is in debug mode, the operation of
BIU is not affected.
9.5.3 Real-Time Signal Client submodule (REDC)
The REDC provides one external time base, imported from the real-time signal bus (also called STAC
bus), to the Unified Channels. Figure 9-40 provides a block diagram for the REDC module.
9-44
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor