PXD10RM Datasheet, PDF (976/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

In anticipation of the low-power mode exit notification, the TDO pad is driven to `1'.
On HALT0 or STOP0 mode exit, the MC_ME asserts the lp_mode_exit_req input after ensuring that the
regulator and memories are in normal mode and before the processor exits its halted or stopped state. The
mode transition will then not proceed until the lp_mode_exit_ack output has been asserted. The MC_RGM
asserts the exit_from_standby input when executing a reset sequence due to a STANDBY0 exit. The reset
sequence will then not complete until the lp_mode_exit_ack output has been asserted.
The notification to the debugger of a low-power mode exit consists of driving the TDO pad to `0'. The
debugger acknowledges that the transition from a low-power mode can continue by setting the low-power
mode sync bit in the port control register (written by debugger), which results in the assertion of the
lp_sync_out input.
NOTE
The debugger clock multiplexer may not guarantee glitch free switching.
Therefore, TCK should be disabled from when the debugger clears the sync
bit in ENTRY_CLR until the debugger senses the falling edge of TDO in
TDO_SET.
26.7.2 Enabling Nexus Clients for TAP Access
After the conditions have been met to bring the NDI out of the reset state, the loading of a specific
instruction in the JTAG controller (JTAGC) block is required to grant the NDI ownership of the TAP. Each
Nexus client has its own JTAGC instruction opcode for ownership of the TAP, granting that client the
means to read/write its registers. The JTAGC instruction opcode for each Nexus client is shown in
Table 26-11. After the JTAGC opcode for a client has been loaded, the client is enabled by loading its
NEXUS-ENABLE instruction. The NEXUS-ENABLE instruction opcode for each Nexus client is listed
in Table 26-12. Opcodes for all other instructions supported by Nexus clients can be found in the relevant
sections of this chapter.
Table 26-11. JTAGC Instruction Opcodes to Enable Nexus Clients
JTAGC Instruction
ACCESS_AUX_TAP_NPC
ACCESS_AUX_TAP_ONCE
Opcode
Description
10000 Enables access to the NPC TAP controller.
10001 Enables access to the e200z0 TAP controller.
Table 26-12. Nexus Client JTAG Instructions
Instruction
Description
NEXUS_ENABLE
BYPASS
NEXUS2_ACCESS
BYPASS
NPC JTAG Instruction Opcodes
Opcode for NPC Nexus ENABLE instruction (4-bits)
Opcode for the NPC BYPASS instruction (4-bits)
e200z0 OnCE JTAG Instruction Opcodes¹
Opcode for e200z0 OnCE Nexus ENABLE instruction
(10-bits)
Opcode for the e200z0 OnCE BYPASS instruction
(10-bits)
Opcode
0x0
0xF
0x7C
0x7F
26-16
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor