PXD10RM Datasheet, PDF (1070/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Table 30-48. Delay Values
Bus Clock 64 MHz
Bus Clock 100 MHz
Delay Prescaler Values
Delay Prescaler Values
2
4
8
16
32
64
128
256
512
1024
2048
4096
8192
16384
32768
65536
1
3
5
7
1
3
5
7
31.25 ns 93.75 ns 156.25 ns 218.75 ns 20.0 ns 60.0 ns 100.0 ns 140.0 ns
62.5 ns 187.5 ns 312.5 ns 437.5 ns 40.0 ns 120.0 ns 200.0 ns 280.0 ns
125 ns 375 ns 625 ns 875 ns 80.0 ns 240.0 ns 400.0 ns 560.0 ns
250 ns 750 ns 1.25 s 1.75 s 160.0 ns 480.0 ns 800.0 ns 1.1 s
500 ns 1.5 s 2.5 s 3.5 s 320.0 ns 960.0 ns 1.6 s 2.2 s
1 s
3 s
5 s
7 s 640.0 ns 1.9 s 3.2 s 4.5 s
2 s
6 s
10 s
14 s
1.3 s 3.8 s 6.4 s 9.0 s
4 s
12 s
20 s
28 s
2.6 s 7.7 s 12.8 s 17.9 s
8 s
24 s
40 s
56 s
5.1 s 15.4 s 25.6 s 35.8 s
16 s
48 s
80 s 112 s 10.2 s 30.7 s 51.2 s 71.7 s
32 s
96 s 160 s 224 s 20.5 s 61.4 s 102.4 s 143.4 s
64 s 192 s 320 s 448 s 41.0 s 122.9 s 204.8 s 286.7 s
128 s 384 s 640 s 896 s 81.9 s 245.8 s 409.6 s 573.4 s
256 s 768 s 1.28 ms 1.8 ms 163.8 s 491.5 s 819.2 s 1.1 ms
512 s 1.5 ms 2.6 ms 3.6 ms 327.7 s 983.0 s 1.6 ms 2.3 ms
1 ms 3.1 ms 5.1 ms 7.2 ms 655.4 s 2.0 ms 3.3 ms 4.6 ms
30.6.4 Oak Family Compatibility with the QuadSPI - SPI Modes Only
Table 30-49 shows the translation of commands written to the TX FIFO command halfword with
commands written to the Command Ram of the Oak family QSPI. The table illustrates how to configure
the QSPI_CTAR registers to match the default cases for the possible combinations of the Oak Family
Control Bits in its Command RAM. The defaults for the Oak Family are based on a system clock of
40MHz. All delay variables below will generate the same delay, or as close a possible, from the QuadSPI
100MHz system clock that an Oak Family part would generate from its 40MHz system clock. For other
system clock frequencies, the customer can recompute the values using Delay Settings - SPI Modes Only.
• For BITSE = 0  8 bits per transfer
• For DT = 0  0.425s delay: For this value, the closest value in the QuadSPI is 0.480s
• For DSCK = 0  1/2 SCK period: For this value, the value for the QuadSPI is 20ns
30-66
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor