PXD10RM Datasheet, PDF (538/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

For both types of memories (RAM and flash), the intent is to generate errors during data write cycles, such
that subsequent reads of the corrupted address locations generate ECC events, either single-bit corrections
or double-bit noncorrectable errors that are terminated with an error response.
The enabling of these error generation modes requires the same SoC-configurable input enable signal (as
that used to enable single-bit correction reporting) be asserted.
See Figure 16-9 and Table 16-10 for the ECC Configuration Register definition.
Register address: ECSM Base + 0x4a
0
R₀
W
RESET: ₀
1
2
3
4
0 FRC1 FR11 0
BI
BI
0
0
0
0
5
6
7
8
0 FRCN FR1 0
CI NCI
0
0
0
0
9
10 11 12 13 14 15
ERRBIT[0:6]
0
0
0
0
0
0
0
= Unimplemented
Figure 16-9. ECC Error Generation (EEGR) Register
Table 16-10. ECC Error Generation (EEGR) Field Descriptions
Name
Description
2
Force RAM Continuous 1-Bit Data Inversions
FRC1BI 0 = No RAM continuous 1-bit data inversions are generated.
1 = 1-bit data inversions in the RAM are continuously generated.
The assertion of this bit forces the RAM controller to create 1-bit data inversions, as defined by the bit
position specified in ERRBIT[0:6], continuously on every write operation.
The normal ECC generation takes place in the RAM controller, but then the polarity of the bit position
defined by ERRBIT is inverted to introduce a 1-bit ECC event in the RAM.
After this bit has been enabled to generate another continuous 1-bit data inversion, it must be cleared
before being set again to properly re-enable the error generation logic.
This bit can only be set if the same SoC configurable input enable signal (as that used to enable single-bit
correction reporting) is asserted.
Note: The only allowable values for the 4 control bit enables {FR11BI, FRC1BI, FRCNCI, FR1NCI} are
{0,0,0,0}, {1,0,0,0}, {0,1,0,0}, {0,0,1,0} and {0,0,0,1}. All other values result in undefined behavior.
16-12
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor