PXD10RM Datasheet, PDF (369/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Field
6–15
DELTA_Y
24–31
DELTA_X
Table 12-19. DISP_SIZE Field Descriptions
Description
Sets the display size vertical resolution (in pixels)
Sets the display size horizontal resolution (in multiples of 16 pixels)
12.3.4.15 HSYN_PARA Register
Figure 12-18 represents the HSYN_PARA register. HSYN_PARA register sets timing parameters related
to the horizontal synchronization signal generation. The fields FP_H, BP_H, and PW_H stand for HSYNC
signal front-porch, back-porch, and active pulse width, respectively.
Offset: 0x1DC
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R0
W
BP_H
00
PW_H[0:3]
Reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
PW_H[4:8]
W
00
FP_H
Reset 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 1
Figure 15.
Figure 12-18. HSYN_PARA Register
Field
1–9
BP_H
12–20
PW_H
23–31
FP_H
Table 12-20. HSYN_PARA Field Descriptions
Description
HSYNC back-porch pulse width (in pixel clock cycles). Pulse width has a minimum value of 1.
HSYNC active pulse width (in pixel clock cycles).
HSYNC front-porch pulse width (in pixel clock cycles). Pulse width has a minimum value of 1.
12.3.4.16 VSYN_PARA Register
Figure 12-19 represents the VSYN_PARA register. VSYN_PARA register sets timing parameters related
to the vertical synchronization signal generation. The fields FP_V, BP_V, and PW_V stand for VSYNC
signal front-porch, back-porch, and active pulse width, respectively.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
12-37