PXD10RM Datasheet, PDF (313/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

11.8.4 DSPI Baud Rate and Clock Delay Generation
The SCK_x frequency and the delay values for serial transfer are generated by dividing the system clock
frequency by a prescaler and a scaler with the option of doubling the baud rate.
Figure 11-13 shows conceptually how the SCK signal is generated.
System Clock
1
Prescaler
1 + DBR
Scaler
SCK_x
Figure 11-13. Communications Clock Prescalers and Scalers
11.8.4.1 Baud Rate Generator
The baud rate is the frequency of the serial communication clock (SCK_x). The system clock is divided
by a baud rate prescaler (defined by DSPIx_CTAR[PBR]) and baud rate scaler (defined by
DSPIx_CTAR[BR]) to produce SCK_x with the possibility of doubling the baud rate. The DBR, PBR, and
BR fields in the DSPIx_CTARs select the frequency of SCK_x using the following formula:
SCK baud rate
=
-----------------------f--^S----^Y----^S-------------------------
PBRPrescalerValue

-----------1-----+-----D-----B----R--------------
BRScalerValue
Table 11-19 shows an example of a computed baud rate.
Table 11-19. Baud Rate Computation Example
f_SYS
PBR
100 MHz
20 MHz
0b00
0b00
Prescaler
Value
2
2
BR
0b0000
0b0000
Scaler
Value
2
2
DBR
Value
0
1
Baud Rate
25 Mb/sec
10 Mb/sec
11.8.4.2 CS to SCK Delay (t_CSC)
The CS_x to SCK_x delay is the length of time from assertion of the CS_x signal to the first SCK_x edge.
Refer to Figure 11-14 for an illustration of the CS_x to SCK_x delay. The PCSSCK and CSSCK fields in
the DSPIx_CTARn registers select the CS_x to SCK_x delay, and the relationship is expressed by the
following formula:
t_CSC =
1 _{ PCSSCK}
f_SYS
 CSSCK
Table 11-20 shows an example of the computed CS to SCK_x delay.
Table 11-20. CS to SCK Delay Computation Example
PCSSCK
0b01
Prescaler
Value
3
CSSCK
0b0100
Scaler
Value
32
f_SYS
100 MHz
CS to SCK Delay
0.96 s
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
11-31