PXD10RM Datasheet, PDF (1060/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

30.5.3.1 Issuing SFM Commands
Each access to the external device follows the same sequence:
1. The user must provide the required components of a SFM command to the QuadSPI module.
2. From these components the complete transaction is built. The transaction starts and the status bit
QSPI_SFMSR[BUSY] is set.
3. Communication with the external serial flash device is started and the transaction is executed.
4. When the transaction is finished (all transmit- and receive operations with the external serial flash
device are finished) or terminated (an error condition occurred during the transaction) the status bit
QSPI_SFMSR[BUSY] is reset and the QSPI_SFMFR[TFF] flag is set.
Further details are given in below in Section 30.5.3.2, Flash Programming” and Section 30.5.3.3, Flash
Read”.
Note that there are 2 different ways to trigger the processing of SFM Commands in the QuadSPI module.
30.5.3.1.1 IP Commands
For IP Commands the required components need to be written into the following registers:
• Read address of the serial flash into QSPI_SFAR, refer to Section 30.4.3.11, Serial Flash Address
Register (QSPI_SFAR)”.
• Instruction code options belonging to the IP Command into the QSPI_ICR[ICO] field.
• Instruction code belonging to the IP Command into the QSPI_ICR[IC] field.
Note that the write into the QSPI_ICR[IC] field must be the last step of the sequence. It is possible
to combine both fields of the QSPI_ICR into one single write. Refer to Section 30.4.3.12,
Instruction Code Register (QSPI_ICR)” for details.
Note that there are some conditions were no IP Command is executed after writing the QSPI_ICR[IC] field
and the write operation itself is ignored. They are described in Section 30.6.7, Command Arbitration -
SFM Mode Only”.
30.5.3.1.2 AHB Commands
Note that the required components of the AHB commands are located in different registers w.r.t. the IP
Commands. They need to be written into the QSPI_ACR register like described in Section 30.4.3.18,
AMBA Control Register (QSPI_ACR)”.
The AHB Command itself is triggered by a read access of the host into the memory mapped serial flash
data, like described in Section 30.4.4.2, Memory Mapped Serial Flash Data (QSPI_SFD)”.
Again the possible error conditions are described in Section 30.6.7, Command Arbitration - SFM Mode
Only”.
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PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor