PXD10RM Datasheet, PDF (1021/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Field
PDT
PBR
CSSCK
ASC
DT
BR
Table 30-11. QSPI_CTARn Field Descriptions (continued)
Descriptions
Delay after Transfer Prescaler. The PDT field selects the prescaler value for the delay between the
negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the
next frame. The PDT field is only used in Master Mode. Table 30-16 lists the prescaler values. See
the DT[0:3] field description for details on how to compute the Delay after Transfer.
00 Delay after Transfer Prescaler value 1
01 Delay after Transfer Prescaler value 3
10 Delay after Transfer Prescaler value 5
11 Delay after Transfer Prescaler value 7
Baud Rate Prescaler. The PBR field selects the prescaler value for the baud rate. This field is only
used in Master Mode. The Baud Rate is the frequency of the Serial Communications Clock (SCK).
The system clock is divided by the prescaler value before the baud rate selection takes place. The
Baud Rate Prescaler values are listed in Table 30-17. See the BR[0:3] field description for details
on how to compute the baud rate.
00 Baud Rate Prescaler value 1
01 Baud Rate Prescaler value 3
10 Baud Rate Prescaler value 5
11 Baud Rate Prescaler value 7
PCS to SCK Delay Scaler. The CSSCK field selects the scaler value for the PCS to SCK delay. This
field is only used in Master Mode. The PCS to SCK Delay is the delay between the assertion of PCS
and the first edge of the SCK. Table 30-14 list the scaler values.The PCS to SCK Delay is a multiple
of the system clock period and it is computed according to the following equation:
t_CSC
=
-----¹-----
f_SYS

PCS
S
CK

CS
S
CK
See Section 30.5.2.7.2, PCS to SCK Delay (tCSC),” for more details.
Eqn. 30-1
After SCK Delay Scaler. The ASC field selects the scaler value for the After SCK Delay. This field is
only used in Master Mode. The After SCK Delay is the delay between the last edge of SCK and the
negation of PCS. Table 30-15 list the scaler values.The After SCK Delay is a multiple of the system
clock period, and it is computed according to the following equation:
t_ASC
=
-----¹-----
f_SYS

PASC

A
S
C
See Section 30.5.2.7.3, After SCK Delay (tASC),” for more details.
Eqn. 30-2
Delay after Transfer Scaler. The DT field selects the Delay after Transfer Scaler. This field is only
used in Master Mode. The Delay after Transfer is the time between the negation of the PCS signal
at the end of a frame and the assertion of PCS at the beginning of the next frame. Table 30-16 lists
the scaler values. In the Continuous Serial Communications Clock operation the DT value is fixed
to one TSCK.
t_DT
=
-----¹-----  PDT  DT
f_SYS
See Section 30.5.2.7.4, Delay after Transfer (tDT),” for more details.
Eqn. 30-3
Baud Rate Scaler. The BR field selects the scaler value for the baud rate. This field is only used in
Master Mode. The pre-scaled system clock is divided by the Baud Rate Scaler to generate the
frequency of the SCK. Table 30-17 lists the Baud Rate Scaler values.
The baud rate is computed according to the following equation:
SCK baud rate
=
-^f--^S---^Y----^S-  ¹-----⁺-----^D-----^B----^R--
PBR BR
See Section 30.5.2.7.1, Baud Rate Generator,” for more details.
Eqn. 30-4
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
30-17