PXD10RM Datasheet, PDF (703/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

• Read the ID field (optional – needed only if a mask was used)
• Read the Data field
• Clear the frames available interrupt (mandatory – release the buffer and allow the CPU to read the
next FIFO entry)
18.4.5 Matching process
The matching process is an algorithm executed by the MBM that scans the MB memory looking for Rx
MBs programmed with the same ID as the one received from the CAN bus. If the FIFO is enabled, the
8-entry ID table from FIFO is scanned first and then, if a match is not found within the FIFO table, the
other MBs are scanned. In the event that the FIFO is full, the matching algorithm will always look for a
matching MB outside the FIFO region.
When the frame is received, it is temporarily stored in a hidden auxiliary MB called Serial Message Buffer
(SMB). The matching process takes place during the CRC field of the received frame. If a matching ID is
found in the FIFO table or in one of the regular MBs, the contents of the SMB will be transferred to the
FIFO or to the matched MB during the 6th bit of the End-Of-Frame field of the CAN protocol. This
operation is called “move-in”. If any protocol error (CRC, ACK, etc.) is detected, than the move-in
operation does not happen.
For the regular mailbox MBs, an MB is said to be “free to receive” a new frame if the following conditions
are satisfied:
• The MB is not locked (see Section 18.4.6.3, Message Buffer Lock Mechanism)
• The Code field is either EMPTY or else it is FULL or OVERRUN but the CPU has already serviced
the MB (read the C/S word and then unlocked the MB)
If the first MB with a matching ID is not “free to receive” the new frame, then the matching algorithm
keeps looking for another free MB until it finds one. If it can not find one that is free, then it will overwrite
the last matching MB (unless it is locked) and set the Code field to OVERRUN (refer to Table 18-5 and
Table 18-6). If the last matching MB is locked, then the new message remains in the SMB, waiting for the
MB to be unlocked (see Section 18.4.6.3, Message Buffer Lock Mechanism).
Suppose, for example, that the FIFO is disabled and there are two MBs with the same ID, and FlexCAN
starts receiving messages with that ID. Let us say that these MBs are the second and the fifth in the array.
When the first message arrives, the matching algorithm will find the first match in MB number 2. The code
of this MB is EMPTY, so the message is stored there. When the second message arrives, the matching
algorithm will find MB number 2 again, but it is not “free to receive”, so it will keep looking and find MB
number 5 and store the message there. If yet another message with the same ID arrives, the matching
algorithm finds out that there are no matching MBs that are “free to receive”, so it decides to overwrite the
last matched MB, which is number 5. In doing so, it sets the Code field of the MB to indicate OVERRUN.
The ability to match the same ID in more than one MB can be exploited to implement a reception queue
(in addition to the full featured FIFO) to allow more time for the CPU to service the MBs. By programming
more than one MB with the same ID, received messages will be queued into the MBs. The CPU can
examine the Time Stamp field of the MBs to determine the order in which the messages arrived.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
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