PXD10RM Datasheet, PDF (217/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

ModulationDepth
=


1_---0_---0_-----_-----5_----_-----I_--N_--2---1C_--5--S_--–--T_---1-E_----P_----x_--M-M_-----D-O_----F-D_----P_----E_----R_----I_---O_-----D_{--}
NOTE
You must ensure that the value of MODPERIOD does not exceed 0x1000
and that the product of INCTEP and MODPERIOD is less than (2¹⁵-1).
Figure 8-23. PLL frequency modulation modes
8.9.6.4 Powerdown mode
The PLL can be switched off when not required to achieve lower consumption by programming the
registers ME_x_MC register on MC_ME module.
8.9.6.5 1:1 Mode (FMPLL0 only)
1:1 Mode is set by asserting the mode bit in CR (see Section 8.9.5.1, Control register (CR)”). An external
input signal (mode_en) has been provided to disable this feature. If mode_en is tied to 0, the mode bit in
CR is disabled and there is no way to activate 1:1 Mode.
In 1:1 Mode the inputs of the PLL are driven by CR and MR, but the division factors and the modulation
parameters have no influence on the output clock. In fact the dividers and the FM control are bypassed
inside the PLL. The PLL output clock (phi) frequency is determined by the following relation:
phi
=
c_---l_---k_---i_--n_-
2
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
8-39