PXD10RM Datasheet, PDF (686/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Base + 0x0004
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R
PRESDIV
RJW
PSEG1
PSEG2
W
RESET: ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16 17 18 19
20
21
22
R _{BOFF ERR_ CLK_ LPB TWRN RWRN 0}
W ^{_MSK MSK SRC}
_MSK _MSK
RESET: ₀
0
0
0
0
0
0
23 24 25 26 27 28 29 30 31
0 SMP BOFF TSYN LBUF LOM
_REC
PROPSEG
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 18-6. Control Register (CTRL)
Table 18-10. Control Register (CTRL) Field Descriptions
Field
Description
0-7
PRESDIV
Prescaler Division Factor
This 8-bit field defines the ratio between the CPI clock frequency and the Serial Clock (Sclock)
frequency. The Sclock period defines the time quantum of the CAN protocol. For the reset value,
the Sclock frequency is equal to the CPI clock frequency. The Maximum value of this register is
0xFF, that gives a minimum Sclock frequency equal to the CPI clock frequency divided by 256. For
more information refer to Section 18.4.8.4, Protocol Timing.
Sclock frequency = CPI clock frequency / (PRESDIV + 1)
8-9
RJW
Resync Jump Width
This 2-bit field defines the maximum number of time quanta¹ that a bit time can be changed by one
resynchronization. The valid programmable values are 0–3.
Resync Jump Width = RJW + 1.
10-12
PSEG1
PSEG1 — Phase Segment 1
This 3-bit field defines the length of Phase Buffer Segment 1 in the bit time. The valid programmable
values are 0–7.
Phase Buffer Segment 1 = (PSEG1 + 1) x Time-Quanta.
13-15
PSEG2
PSEG2 — Phase Segment 2
This 3-bit field defines the length of Phase Buffer Segment 2 in the bit time. The valid programmable
values are 1–7.
Phase Buffer Segment 2 = (PSEG2 + 1) x Time-Quanta.
16
BOFF_MSK
Bus Off Mask
This bit provides a mask for the Bus Off Interrupt.
1= Bus Off interrupt enabled
0 = Bus Off interrupt disabled
18-16
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor