PXD10RM Datasheet, PDF (971/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

NOTE
The EOC bits in DC1 must be programmed to trigger EVTO on watchpoint
occurrence for the EWC bits to have any effect.
26.6.2.4 Development Status Register (DS)
The development status register is used to report system debug status. When debug mode is entered or
exited, or a core-defined low-power mode is entered, a debug status message is transmitted with
DS[31:24]. The external tool can read this register at any time.
Nexus 0x0004
Reg:
0
1
2
3
R _DBG
LPS
W
Reset ₀
0
0
0
4
5
6
7
LPC
CHK 0
0
0
0
0
Access: User read only
8
9
10 11 12 13 14 15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23 24 25 26 27 28 29 30 31
R₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 26-7. Development Status Register (DS)
Table 26-7. DS Field Descriptions
Field
0
DBG
CPU Debug Mode Status.
0 CPU not in debug mode.
1 CPU in debug mode.
1–3 System Low Power Status
LPS 000 Normal (run) mode
xx1 Doze mode
x1x Nap mode
1xx Sleep mode
4–5
LPC[1:0]
CPU Low-Power Mode Status.
00 Normal (run) mode.
01 CPU in halted state.
10 CPU in stopped state.
11 Reserved.
6
CHK
CPU Checkstop Status.
0 CPU not in checkstop state.
1 CPU in checkstop state.
7–31 Reserved.
Description
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
26-11