PXD10RM Datasheet, PDF (263/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

MODE _[6=_]1
cycle n
write to A2
Match A1
Match B1
internal counter
0x8
0x6
0x4
0x2
0x1
due to B1 match cycle n-1
Output pin
FLAG set event
FLAG pin/register
FLAG clear
cycle n+1
write to A2
Match A1
write to B2
Match B1
cycle n+2
Match B1
A1/B1 load signal
A1 value¹ 0x2
0x4
A2 value¹ 0x2
0x4
0x6
0x6
EDPOL = 0
Prescaler ratio = 4
B1 value 0x8
B2 value 0x8
0x6
0x6
Figure 9-31. OPWFMB A1 and B1 Registers Update and Flags
Figure 9-32 describes the operation of the Output Disable feature in OPWFMB mode. The output disable
forces the channel output flip-flop to EDPOL bit value. This functionality targets applications that use
active high signals and a high to low transition at A1 match. In this case EDPOL should be set to 0. Note
that both the channel and global prescalers are set to 0x0 (each divide ratio is one), meaning that the
channel internal counter transitions at every system clock cycle.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
9-37