PXD10RM Datasheet, PDF (491/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Name
NOP
CERR[0:6]
Table 15-11. DMA Clear Error (DMACERR) field descriptions
Description
No Operation
Clear Error Indicator
Value
0 Normal operation.
1 No operation, ignore bits 6-0
0-63 Clear corresponding bit in DMAERR{H,L}
64-127 Clear all bits in DMAERR{H,L}
15.2.1.11 DMA Set START Bit (DMASSRT)
The DMASSRT register provides a simple memory-mapped mechanism to set the START bit in the TCD
of the given channel. The data value on a register write causes the START bit in the corresponding Transfer
Control Descriptor to be set. A data value of 64 to 127 (regardless of the number of implemented channels)
provides a global set function, forcing all START bits to be set. If bit 7 is set, the command is ignored. This
allows multiple byte registers to be written as a 32-bit word. Reads of this register return all zeroes. See
Table 15-28 for the TCD START bit definition.
Register address: DMA_Offset + 0x001e
0
1
2
3
4
5
6
7
R
0
0
0
0
0
0
0
0
W
NOP
SSRT[0:6]
RESET:
0
0
0
0
0
0
0
Name
NOP
SSRT[0:6]
= Unimplemented
Figure 15-12. DMA Set START Bit (DMASSRT) Register
Table 15-12. DMA Set START Bit (DMASSRT) field descriptions
Description
No Operation
Set START Bit
(Channel Service Request)
Value
0 Normal operation.
1 No operation, ignore bits 6-0
0-63 Set the corresponding channel’s TCD.start
64-127 Set all TCD.start bits
15.2.1.12 DMA Clear DONE Status (DMACDNE)
The DMACDNE register provides a simple memory-mapped mechanism to clear the DONE bit in the
TCD of the given channel. The data value on a register write causes the DONE bit in the corresponding
Transfer Control Descriptor to be cleared. A data value of 64 to 127 (regardless of the number of
implemented channels) provides a global clear function, forcing all DONE bits to be cleared. If bit 7 is set,
the command is ignored. This allows multiple byte registers to be written as a 32-bit word. Reads of this
register return all zeroes. See Table 15-28 for the TCD DONE bit definition.
Register address: DMA_Offset + 0x001f
0
1
2
3
4
5
6
7
R
0
0
0
0
0
0
0
0
W
NOP
CDNE[0:6]
RESET:
0
0
0
0
0
0
0
= Unimplemented
Figure 15-13. DMA Clear DONE Status (DMACDNE) Register
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
15-21