PXD10RM Datasheet, PDF (609/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Table 17-43. MCR bits set/clear priority levels
Priority level
1
2
3
4
MCR bits
ERS
PGM
EHV
ESUS
If the user attempts to write two or more MCR bits simultaneously then only the bit with the lowest priority
level will be written.
17.3.6.2 Low/Mid address space block Locking register (LML)
Address Offset: 0x0004
Reset value: 0x00XXXXXX, initially determined by NVLML value from test sector.
17.3.6.3 Non-volatile Low/Mid address space block Locking register (NVLML)
Address Offset: 0x403DE8
Delivery value: 0xFFFFFFFF
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
LME
0
0
0
0
0
0
0
0
0
0 TSLK 0
0 MLK1 MLK0
r/0
r/0
r/0
r/0
r/0
r/0
r/0
r/0
r/0
r/0
r/0 rw/X r/0
r/0 rw/X rw/X
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
LLK15 LLK14 LLK13 LLK12 LLK11 LLK10 LLK9 LLK8 LLK7 LLK6 LLK5 LLK4 LLK3 LLK2 LLK1 LLK0
rw/X rw/X rw/X rw/X rw/X rw/X rw/X rw/X rw/X rw/X rw/X rw/X rw/X rw/X rw/X rw/X
Figure 17-28. Non-volatile Low/Mid address space block Locking register (NVLML)
The Low/Mid Address Space Block Locking register provides a means to protect blocks from being
modified. These bits, along with bits in the SLL register, determine if the block is locked from Program or
Erase. An “OR” of LML and SLL determine the final lock status.
The LML register has a related non-volatile Low/Mid Address Space Block Locking register located in
Test Flash that contains the default reset value for LML: The NVLML register is read during the reset
phase of the Flash Module and loaded into the LML.
The NVLML register is a 64-bit register, the 32 most significative bits of which (bits 63-32) are ‘don’t
care’ and eventually used to manage ECC codes.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
17-59