PXD10RM Datasheet, PDF (1181/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Table 36-12. Generation of the ‘Resulting DCOIL’
BLNST BLNDCL
ITGST
ITGDCL
Resulting
DCOIL
Remarks
0
x
0
0
0
1
1
1
0
0
x
0
1
1
0
x
1
0
0
1
1
No running BIS
ITGDCL determines result
Running BIS in blanking phase
BLNDCL determines result
Running BIS in integration phase
ITGDCL determines result
36.4.1.2.2 Switch Condition States
The analog switches S1 to S8 are used to select the appropriate source and polarity of the non-driven coil
into the -modulator for integration during the integration phase of an ongoing BIS. Outside of the
integration phase none of the switches is enabled. Refer to Table 36-13 below for details.
Table 36-13. Switch Condition States
ITGST
0
1
1
1
1
1
1
1
1
STEP
(Register
Bit)
Integration Polarity
(Input to analog block)
S1
S2
S3
S4
S5
S6
S7
S8
xx
x
Open Open Open Open Open Open Open Open
00
0
Open Open Open Open Close Open Open Close
00
1
Open Open Open Open Open Close Close Open
01
0
Open Close Close Open Open Open Open Open
01
1
Close Open Open Close Open Open Open Open
10
0
Open Open Open Open Open Close Close Open
10
1
Open Open Open Open Close Open Open Close
11
0
Close Open Open Close Open Open Open Open
11
1
Open Close Close Open Open Open Open Open
NOTE
The value given in the column ‘Integration Polarity’ in Table 36-13 is linked
to the ITGDIR bit in the CONTROL register in the way described in
Section 36.4.1.4.3, DC Offset Cancellation” below.
36.4.1.3 Register Interface
The register interface processes the IPS accesses from the device level. Access size is 32 bits, the SSD
block supports 16- and 32-bit accesses.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
36-15