PXD10RM Datasheet, PDF (862/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Field
DATA7[0:7]
0:7
DATA6[0:7]
8:15
DATA5[0:7]
16:23
DATA4[0:7]
24:31
Table 23-22. BDRM field descriptions
Data Byte 7
Data byte 7 of the data field.
Data Byte 6
Data byte 6 of the data field.
Data Byte 5
Data byte 5 of the data field.
Data Byte 4
Data byte 4 of the data field.
Description
23.7.2.17 Identifier filter enable register (IFER)
This register is not implemented on LINFlex_1.
Address: Base + 0x0040
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0 0 0 0 0 0 0 0
W
FACT[0:7]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 23-23. Identifier filter enable register (IFER)
Table 23-23. IFER field descriptions
Field
0:23
FACT[0:7]
24:31
Description
Reserved
Filter activation
0 Filters 2n and 2n + 1 are activated.
1 Filters 2n and 2n + 1 are deactivated.
(Refer to Table 23-24.)
These bits can be set/cleared in Initialization mode only.
Bit
FACT[0]
Table 23-24. IFER[FACT] configuration
Value
0
1
Result
Filters 0 and 1 are deactivated.
Filters 0 and 1 are activated.
23-30
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor