PXD10RM Datasheet, PDF (265/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

EMIOSCNT
0x000008
cycle 1
cycle 2
cycle 3
cycle 4
cycle 5
cycle 6
cycle 7
cycle 8
cycle 9
0x000001
Output pin
100%
0%
A1 value
A2 value
B1 value
EDPOL = 0
Prescaler ratio = 1
0x000008 0x000007 0x000006 0x000005 0x000004 0x000003 0x000002 0x000001 0x000000
0x000007 0x000006 0x000005 0x000004 0x000003 0x000002 0x000001 0x000000
0x000008
Figure 9-33. OPWFMB Mode from 100% to 0% Duty Cycle
A 0% duty cycle signal is generated if A1=0x0 as shown in Figure 9-33 cycle 9. In this case B1=0x8 match
from cycle 8 occurs at the same time as the A1=0x0 match from cycle 9. See Figure 9-30 for a description
of the A1 and B1 match generation. In this case A1 match has precedence over B1 match and the output
signal transitions to EDPOL.
9.5.1.1.6 Output Pulse Width Modulation Buffered (OPWMB) Mode
OPWMB mode (MODE[0:6]=11000b0) is used to generate pulses with programmable leading and trailing
edge placement. An external counter driven in MCB Up mode must be selected from one of the counter
buses. A1 register value defines the first edge and B1 the second edge. The output signal polarity is defined
by the EDPOL bit. If EDPOL is zero, a negative edge occurs when A1 matches the selected counter bus;
and a positive edge occurs when B1 matches the selected counter bus.
The A1 and B1 registers are double buffered and updated from A2 and B2, respectively, at the cycle
boundary. The load operation is similar to the OPWFMB mode. See Figure 9-31 for more information
about A1 and B1 registers update.
FLAG can be generated at B1 matches, when MODE[5] is cleared, or in both A1 and B1 matches, when
MODE[5] is set. If subsequent matches occur on comparators A and B, the PWM pulses continue to be
generated, regardless of the state of the FLAG bit.
FORCMA and FORCMB bits allow the software to force the output flip-flop to the level corresponding
to a match on A1 or B1 respectively. FLAG bit is not set by the FORCMA and FORCMB operations.
At OPWMB mode entry the output flip-flop is set to the value of the EDPOL bit in the EMIOSC[n]
register.
Following are described some rules applicable to the OPWMB mode:
• B1 matches have precedence over A1 matches if they occur at the same time within the same
counter cycle
• A1=0 match from cycle n has precedence over B1 match from cycle n-1
• A1 matches are masked out if they occur after B1 match within the same cycle
• Any value written to A2 or B2 on cycle n is loaded to A1 and B1 registers at the following cycle
boundary (assuming OU[n] bit of EMIOSOUDIS register is not asserted). Thus the new values will
be used for A1 and B1 matches in cycle n+1
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
9-39