PXD10RM Datasheet, PDF (252/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

The eMIOS200 block is reset asynchronously. All registers are cleared on reset.
Figure 9-18 describes an eMIOS200 block configured with 32 Unified Channels. Note that the RedLine is
also present. Note also that independent of the configuration the channels are fixed in their slots, thus for
exempla if channel [2] is not required this location will be empty, meaning that the other channels locations
are not affected. In this case the application software should not access any register located in the
channel[2] memory. Any attempt to access those registers will return no meaningful data and a Transfer
Error will be generated .
Real-time signals
Enhanced Modular I/O Subsystem
emios200
(former STAC Bus)
IP
Interface
BIU
All
channels
GTBE_OUT
Global
regs
GTBE_IN
All channels
bus [D]
channel[23]
channel[16]
bus [C]
channel[15]
EMIOS[23]
EMIOS[16]
EMIOS[15]
system
clock
Global
Prescaler
All
channels
channel[8]
bus [B]
channel[7]
EMIOS[8]
EMIOS[7]
channel[0]
EMIOS[0]
output disable inputs[3:0]
Figure 9-18. eMIOS200 Full Channel Configuration using Unified Channels only
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PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor