PXD10RM Datasheet, PDF (237/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Table 9-9. EMIOSMCR field descriptions
Field
MDIS
FRZ
GTBE
Description
Module Disable
Puts the eMIOS200 in low power mode. The MDIS bit is used to stop the clock of the block, except
the access to registers EMIOSMCR, EMIOSOUDIS and EMIOSUCDIS.
1 = Enter low power mode
0 = Clock is running
Freeze
Enable the eMIOS200 to freeze the registers of the Unified Channels when the MCU is stopped by
a debugger. Each Unified Channel should have FREN bit set in order to enter freeze state. While in
Freeze state, the eMIOS200 continues to operate to allow the MCU access to the Unified Channels
registers. The Unified Channel will remain frozen until the FRZ bit is written to zero or the MCU exits
Debug mode or the Unified Channel FREN bit is cleared.
1 = Stops Unified Channels operation when in Debug mode and the FREN bit is set in the EMIOSC[n]
register
0 = Exit freeze state
Global Time Base Enable
The GTBE bit is used to export a Global Time Base Enable from the module and provide a method
to start time bases of several blocks simultaneously.
1 = Global Time Base Enable Out signal asserted
0 = Global Time Base Enable Out signal negated
ETB
GPREN
SRV
GPRE
Note: The Global Time Base Enable input pin controls the internal counters. When asserted, Internal
counters are enabled. When negated, Internal counters disabled.
External Time Base
The ETB bit selects the time base source that drives counter bus[A].
1 = Counter bus[A] assigned to REDC
0 = Counter bus[A] assigned to Unified Channel
Global Prescaler Enable
The GPREN bit enables the prescaler counter.
1 = Prescaler enabled
0 = Prescaler disabled (no clock) and prescaler counter is cleared
Server Time Slot
The SRV[0:3] bits select the address of a specific real-time signal server to which the REDC is
assigned (refer to Section 9.5.3, Real-Time Signal Client submodule (REDC),” for details).
Global Prescaler
The GPRE[0:7] bits select the clock divider value for the global prescaler, as shown in Table 9-10.
Table 9-10. Global Prescaler clock divider
GPRE[0:7]
00000000
00000001
00000010
00000011
Divide ratio
1
2
3
4
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
9-11