PXD10RM Datasheet, PDF (1028/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Field
CONT
CTAS
Table 30-20. QSPI_PUSHR Field Descriptions
Descriptions
Continuous Peripheral Chip Select Enable. The CONT bit selects a Continuous Selection Format.
The bit is used in SPI Master Mode. The bit enables the selected PCS signals to remain asserted
between transfers. See Section 30.5.2.8.5, Continuous Selection Format,” for more information.
0 Return Peripheral Chip Select signals to their inactive state between transfers
1 Keep Peripheral Chip Select signals asserted between transfers
Clock and Transfer Attributes Select. The CTAS field selects which of the QSPI_CTAR register is
used to set the clock and transfer attributes for the associated SPI frame. The field is only used in SPI
Master Mode. In SPI Slave Mode QSPI_CTAR0 is used. The table below shows how the CTAS values
map to the QSPI_CTAR registers. All values not given below are reserved.
000 QSPI_CTAR0
001 QSPI_CTAR1
EOQ
CTCNT
PCSx
TXDATA
End Of Queue. The EOQ bit provides a means for host software to signal to the QuadSPI that the
current SPI transfer is the last in a queue. At the end of the transfer the EOQF bit in the QSPI_SPISR
is set.
0 The SPI data is not the last data to transfer
1 The SPI data is the last data to transfer
Clear SPI_TCNT. The CTCNT provides a means for host software to clear the SPI transfer counter.
The CTCNT bit clears the SPI_TCNT field in the QSPI_TCR register. The SPI_TCNT field is cleared
before transmission of the current SPI frame begins.
0 Do not clear SPI_TCNT field in the QSPI_TCR
1 Clear SPI_TCNT field in the QSPI_TCR
Peripheral Chip Select 0–7. The PCS bits select which PCS signals will be asserted for the transfer.
0 Negate the PCSx signal
1 Assert the PCSx signal
TX Data.
Writing the TXDATA field pushed the SPI data to be transferred onto the TX FIFO.
Reading the TXDATA field provides the value which was written most recently into the TXDATA field.
After the TX FIFO has been cleared the result is undefined.
30.4.3.8 POP RX FIFO Register (QSPI_POPR)
The QSPI_POPR provides a means to read the RX FIFO. See Section 30.5.2.6, Receive First In First Out
(RX FIFO) Buffering Mechanism,” for a description of the RX FIFO operations. Eight or sixteen bit read
accesses to the QSPI_POPR will read from the RX FIFO and update the counter and pointer. Refer to
Table 30-45 for the byte ordering scheme.
30-24
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor