PXD10RM Datasheet, PDF (152/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

5.4.6 Conversion timing registers CTR[1..2]
The 0 to 31 range shown below is the maximum range for the channel type. For the exact number of
available channels, please refer to Table 5-5.
CTR1 = associated to extended internal channels (from 32 to 63)
CTR2 = associated to external channels (from 64 to 95)
Address: Base + 0x0098 (CTR1)
Base + 0x009C (CTR2)
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
0 _OFFSHIFT 0 _INPCMP 0
W
[0:1]
[0:1]
INPSAMP[0:7]
Reset 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1
Figure 5-20. Conversion timing registers CTR[1..2]
Table 5-19. Conversion timing registers CTR[1..2] field descriptions
Field
0:15
16
17
18:19
20
21:22
23
Description
Reserved
Write of any value has no effect, read value is always 0.
INPLATCH
Configuration bit for latching phase duration
Reserved
Write of any value has no effect, read value is always 0.
OFFSHIFT[0:1]
Configuration for offset shift characteristic
00 No shift (that is the transition between codes 000h and 001h) is reached when the A_VIN (analog input
voltage) is equal to 1 LSB.
01 Transition between code 000h and 001h is reached when the A_VIN is equal to1/2 LSB
10 Transition between code 00h and 001h is reached when the A_VIN is equal to 0
11 Not used
Reserved
Write of any value has no effect, read value is always 0.
INPCMP[0:1]
Configuration bits for comparison phase duration
Reserved
Write of any value has no effect, read value is always 0.
5-30
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor