PXD10RM Datasheet, PDF (639/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

• Dual AHB input port interfaces support a 32-bit data bus. All AHB aligned and unaligned reads
within the 32-bit container are supported. Only aligned word writes are supported.
• Array interfaces support a 128-bit read data bus and a 64-bit write data bus for each of the 3 banks
• Internal hardware structure supports fully concurrent accesses from the dual AHB input ports when
accessing different flash banks
— If the AHB ports reference the same flash bank, there is arbitration logic which determines the
order the accesses are granted access to the bank
— Programmable arbitration allows the user to select fixed priority or round-robin
• Total flash page storage in the PFLASH2P_LCA includes four 4-entry page buffers (b0_p0, b0_p1,
b2_p0, b2_p1) and two 128-bit temporary holding registers (b1_p0, b1_p1).
— Each AHB input port provides configurable and independent read buffering and page prefetch
support for banks 0 and 2
— Each AHB input port includes four page read buffers (each 128 bits wide) and a prefetch
controller to support single-cycle read responses (zero AHB data phase wait-states) for hits in
the buffers. The buffers implement a least-recently-used replacement algorithm to maximize
performance.
— Each AHB input port interfaces to the optional data flash (bank1) includes a 128-bit register to
temporarily hold a single flash page. This logic supports single-cycle read responses (zero
AHB data phase wait-states) for accesses that hit in the holding register. There is no support for
prefetching associated with this bank.
• Programmable response for read-while-write sequences including support for stall-while-write,
optional stall notification interrupt, optional flash operation abort, and optional abort notification
interrupt
• Separate and independent configurable access timing (common settings for banks 0 and 2, separate
settings for bank1) to support use across a wide range of platforms and frequencies
• Support of address-based read access timing for emulation of other memory types
• Support for reporting of single- and multi-bit flash ECC events
• Typical operating configuration loaded into programming model by system reset
Figure 17-43 shows a simplified block diagram of the PFLASH2P_LCA memory controller.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
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