PXD10RM Datasheet, PDF (1062/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

The communication with the external serial flash is stopped when the specified number of bytes
has been read (successful completion of the transaction) or if the RX Buffer overrun condition is
detected (signalled by setting the QSPI_SFMFR[RBOF] flag). In this case the transaction leading
to the RX Buffer overrun is terminated.
• AHB Command Read: For a memory mapped flash read the user must setup a read access to
the address range were the external serial flash device is mapped to by programming the
QSPI_ACR register with the requested data not already available in the AHB Buffer.
On each AHB read access to the memory mapped area the valid data in the AHB Buffer are
checked against the address requested in the actual read. When the AHB read request can’t be
served from the content of the AHB Buffer the complete transaction to access the external serial
flash device is built from the QSPI_ACR register contents and started. The requested number of
bytes defined in the QSPI_ACR[ARSZ] field is then fetched from the external serial flash device
into the internal AHB Buffer. Since the read access is triggered via the AHB bus the AHB_ACC
status bit is set driving in turn the BUSY bit (both are located in the QSPI_SFMSR register) until
the transaction is finished. The communication with the external serial flash is stopped when the
specified number of bytes has been read.
Basically the AHB buffer behaves similar to a cache memory with a size of one single line.
30.5.3.3.2 Host Read of the QuadSPI Module Internal Buffers
The data read out from the external serial flash device by the QuadSPI module are stored in the internal
buffers. Depending from the buffer to which the data from the external serial flash has been loaded there
are several different ways to access these data in the internal buffers:
• Flag-based Data Read of the 1RX Buffer is done by reading the address QSPI_ARDB, see
Section 30.4.4.3, AHB RX Data Buffer (QSPI_ARDB)”.
The QSPI_SFMSR[RXNE] bit indicates that data are available in the RX Buffer and can be read
by AHB read access to address QSPI_ARDB. The RX Buffer is implemented as circular buffer.
This means that after the increment of the read pointer the next read accesses to that (same) address
provides the next data word from the serial flash device. The increment of the read pointer itself is
done by writing a ‘1’ into the QSPI_SFMFR[RBDF] bit.
For the remaining status related bits QSPI_SPISR[RFOF] and QSPI_SPISR[RFDF] refer to
Section 30.4.3.5, SPI Status Register (QSPI_SPISR)”. It’s up to the user to decide whether the
relevant flags are polled by software or to drive the data read by the interrupt capabilities of the
QuadSPI module.
• DMA triggered Data Read of the RX Buffer is done by reading address QSPI_ARDB, see
Section 30.4.4.3, AHB RX Data Buffer (QSPI_ARDB)” by using the DMA capabilities of the
QuadSPI and the device containing the QuadSPI module. The circular buffer pointer is updated
automatically without interaction from the application.
Refer to reference Semiconductor Reuse Standard V3.2 Section 04 IP Interface for details about
the DMA usage. The application must ensure that the DMA controller of the related device is
programmed appropriately.
• RX Buffer, data read via IPS registers: By reading the RX Buffer Data Registers 0–14
(QSPI_RBDR0–QSPI_RBDR14) the individual entries in the RX Buffer can be accessed
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PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor