PXD10RM Datasheet, PDF (223/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Table 8-33. Control Status Register (CMU_CSR) field descriptions
Field
Description
8
SFM
Start frequency measure
The software can only set this bit to start a clock frequency measure. It is reset by
hardware when the measure is ready in the CMU_FDR register.
0: Frequency measurement is completed or not yet started.
1: Frequency measurement is not completed.
22-23
CKSEL1
RC Oscillator(s) selection bit
CKSEL1 selects the clock to be measured by the frequency meter.
00: CK_FIRC is selected.
01: CK_SIRC is selected.
10: CK_SXOSC crystal Oscillator clock is selected.
11: CK_FIRC is selected.
29-30
RCDIV[1:0
]
RC clock division factor
These bits specify the RC clock division factor. The output clock is CK_IRC_fast divided by
the factor 2^RCDIV. This output clock is used to compare with CK_FXOSC for crystal clock
monitor feature.The clock division coding is as follows.
00: Clock divided by 1 (No division)
01: Clock divided by 2
10: Clock divided by 4
11: Clock divided by 8
31
CME_A
FMPLL0 clock monitor enable
0: FMPLL0 monitor is disabled.
1: FMPLL0 monitor is enabled.
8.10.5.2 Frequency Display Register (CMU_FDR)
.
Address offset: 0x04
Reset value: 0x00000000
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
reserved
FD[19:16]
r
r
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
FD[15:0]
r
Table 8-34. Frequency Display Register (CMU_FDR)
Table 8-35. Frequency Display Register (CMU_FDR) field descriptions
Field
12-31
FD
Description
Measured frequency bits
This register displays the measured frequency FRC with respect to FOSC. The measured
value is given by the following formula: FRC = (FOSC * MD) / n, Where n is the value in
CMU_FDR register
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
8-45