PXD10RM Datasheet, PDF (508/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Table 15-28. TCDn Word 7 (TCDn.{biter, control/status}) field descriptions (continued)
Name
major.e_link
Description
Enable channel-to-channel linking
on major loop complete
Value
As the channel completes the outer major loop, this
flag enables the linking to another channel, defined
by major.linkch[5:0]. The link target channel initiates
a channel service request via an internal mechanism
that sets the TCD.start bit of the specified channel. To
support the dynamic linking coherency model, this
field is forced to zero when written to while the
TCD.done bit is set.
e_sg
Enable scatter/gather processing
0 The channel-to-channel linking is disabled.
1 The channel-to-channel linking is enabled.
As the channel completes the outer major loop, this
flag enables scatter/gather processing in the current
channel. If enabled, the DMA engine uses dlast_sga
as a memory pointer to a 0-modulo-32 address
containing a 32-byte data structure which is loaded as
the transfer control descriptor into the local memory.
To support the dynamic scatter/gather coherency
model, this field is forced to zero when written to while
the TCD.done bit is set.
d_req
Disable request
0 The current channel’s TCD is “normal” format.
1 The current channel’s TCD specifies a scatter
gather format. The dlast_sga field provides a
memory pointer to the next TCD to be loaded into
this channel after the outer major loop completes
its execution.
If this flag is set, the DMA hardware automatically
clears the corresponding DMAERQ bit when the
current major iteration count reaches zero.
int_half
0 The channel’s DMAERQ bit is not affected.
1 The channel’s DMAERQ bit is cleared when the
outer major loop is complete.
Enable an interrupt when major counter
is half complete
If this flag is set, the channel generates an interrupt
request by setting the appropriate bit in the DMAINT
register when the current major iteration count
reaches the halfway point. Specifically, the
comparison performed by the DMA engine is (citer ==
(biter >> 1)). This halfway point interrupt request is
provided to support double-buffered schemes or
other types of data movement where the processor
needs an early indication of the transfer’s progress.
The halfway complete interrupt is disabled when biter
values are less than two.
0 The half-point interrupt is disabled.
1 The half-point interrupt is enabled.
15-38
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor