PXD10RM Datasheet, PDF (1081/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Table 30-54. Sampling Configuration
Sampling
Point
Description
N/1
sampling with non-inverted clock, 1 sample delay
I/1
sampling with inverted clock, 1 sample delay
N/2
sampling with non-inverted clock, 2 samples delay
I/2
sampling with inverted clock, 2 samples delay
1_{‘x’ is not considered here}
Delay
[FSDLY]
[HSDLY]
0
0
1
1
Phase
[FSPHS]
[HSPHS]
QSPI_SMPR for
Full Speed
Setting¹
0
0x0000000x
1
0x0000002x
0
0x0000004x
1
0x0000006x
Depending from the actual delay and the serial flash clock frequency the appropriate sampling point can
be chosen. The following remarks should be considered when selecting the appropriate setting:
• Theoretically there should be 2 settings possible to capture the correct data since the serial flash
output is valid for 1 clock cycle, disregarding rise and fall times and timing uncertainties.
• Depending from the timing uncertainties it may turn out in actual applications that only one
possible sample positions remains. This is subject to careful consideration depending from the
actual implementation.
• The delay t_Del,total is an absolute size to shift the point in time when the serial flash date get valid
at the QuadSPI input.
• For decreasing frequency of the serial flash clock the distance between the edges increases. So for
large differences in the frequency the required setting may change.
• For commands running at half of the regular serial flash clock (QSPI_SMPR[HSENA] bit set) the
sampling point must be figured separately to allow for the compensation of the absolute shift in
time w.r.t. the sample-relative setting in the QSPI_SPMPR register.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
30-77