PXD10RM Datasheet, PDF (714/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

• Read and write access to unimplemented or reserved address space also results in access error. Any
access to unimplemented MB or Rx Individual Mask Register locations results in access error. Any
access to the Rx Individual Mask Register space when the BCC bit in MCR is negated results in
access error.
• If MAXMB is programmed with a value smaller than the available number of MBs, then the
unused memory space can be used as general purpose RAM space. Note that the Rx Individual
Mask Registers can only be accessed in Freeze Mode, and this is still true for unused space within
this memory. Note also that reserved words within RAM cannot be used. As an example, suppose
FlexCAN is configured with 64 MBs and MAXMB is programmed with zero. The maximum
number of MBs in this case becomes one. The MB memory starts at 0x0060, but the space from
0x0060 to 0x007F is reserved (for SMB usage), and the space from 0x0080 to 0x008F is used by
the one MB. This leaves us with the available space from 0x0090 to 0x047F. The available memory
in the Mask Registers space would be from 0x0884 to 0x097F.
NOTE
Unused MB space must not be used as general purpose RAM while
FlexCAN is transmitting and receiving CAN frames.
18.5 Initialization/application information
This section provide instructions for initializing the FlexCAN module.
18.5.1 FlexCAN initialization sequence
The FlexCAN module may be reset in three ways:
• MCU level hard reset, which resets all memory mapped registers asynchronously
• MCU level soft reset, which resets some of the memory mapped registers synchronously (refer to
Table 18-2 to see what registers are affected by soft reset)
• SOFT_RST bit in MCR, which has the same effect as the MCU level soft reset
Soft reset is synchronous and has to follow an internal request/acknowledge procedure across clock
domains. Therefore, it may take some time to fully propagate its effects. The SOFT_RST bit remains
asserted while soft reset is pending, so software can poll this bit to know when the reset has completed.
Also, soft reset can not be applied while clocks are shut down in any of the low power modes. The low
power mode should be exited and the clocks resumed before applying soft reset.
The clock source (CLK_SRC bit) should be selected while the module is in Disable Mode. After the clock
source is selected and the module is enabled (MDIS bit negated), FlexCAN automatically goes to Freeze
Mode. In Freeze Mode, FlexCAN is un-synchronized to the CAN bus, the HALT and FRZ bits in MCR
Register are set, the internal state machines are disabled and the FRZ_ACK and NOT_RDY bits in the
MCR Register are set. The Tx pin is in recessive state and FlexCAN does not initiate any transmission or
reception of CAN frames. Note that the Message Buffers and the Rx Individual Mask Registers are not
affected by reset, so they are not automatically initialized.
18-44
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor