PXD10RM Datasheet, PDF (264/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

MODE _[6=_]1
cycle n
write to A2
Match A1
Match B1
internal counter
cycle n+1
write to A2
Match A1
Match B1
write to B2
cycle n+2
Match B1
0x000008
0x000006
0x000004
0x000002
0x000001
due to B1 match cycle n-1
Output pin
FLAG set event
FLAG pin/register
FLAG set event
Output Disable
A1 value 0x000002
A2 value 0x000002
0x000004
0x000004
0x000006
0x000006
EDPOL = 0
Prescaler ratio = 1
B1 value 0x000008
B2 value 0x000008
0x000006
0x000006
Figure 9-32. OPWFMB Mode with Active Output Disable
Note that the output disable has a synchronous operation, meaning that the assertion of the Output Disable
input pin causes the channel output flip-flop to transition to EDPOL at the next system clock cycle. If the
Output Disable input is deasserted the output pin transition at the following A1 or B1 match.
In Figure 9-32 it is assumed that the Output Disable input is enabled and selected for the Channel. See
Section 9.4.2.8, eMIOS200 UC Control Register (EMIOSC[n]),” for a detailed description about the ODIS
and ODISSL bits, respectively enable and selection of the Output Disable inputs.
The FORCMA and FORCMB bits allow the software to force the output flip-flop to the level
corresponding to a match on comparators A or B respectively. Similarly to a B1 match FORCMB sets the
internal counter to 0x1. The FLAG bit is not set by the FORCMA or FORCMB bits being asserted.
Figure 9-33 describes the generation of 100% and 0% duty cycle signals. It is assumed EDPOL =0 and the
resultant prescaler value is 1. Initially A1=0x8 and B1=0x8. In this case, B1 match has precedence over
A1 match, thus the output flip-flop is set to the complement of EDPOL bit. This cycle corresponds to a
100% duty cycle signal. The same output signal can be generated for any A1 value greater or equal to B1.
9-38
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor