PXD10RM Datasheet, PDF (143/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Address: Base + 0x001C
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 5-9. Channel Pending Register 2 (CEOCFR2)
Table 5-10. Channel Pending Registers (CEOCFR[1..2]) field descriptions
Field
31
n
Description
EOC_CH0
When set, the measure of channel 0 is completed.
EOC_CHn
When set, the measure of channel n is completed.
5.4.3.3 Interrupt Mask Register (IMR)
The Interrupt Mask Register (IMR) contains the interrupt enable bits for the ADC.
Address: Base + 0x0020
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 5-10. Interrupt Mask Register (IMR)
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
5-21