PXD10RM Datasheet, PDF (1250/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Address Offset
0x0020 - 0x0027
0x0028
0x002C
0x0030
0x0034
0x0038 - 0x03FFF
Table 41-2. WKPU Memory Map (continued)
Use
Reserved
Wakeup/Interrupt Rising-Edge Event Enable
Register
Wakeup/Interrupt Falling-Edge Event Enable
Register
Wakeup/Interrupt Filter Enable Register
Wakeup/Interrupt Pullup Enable Register
Reserved
Abbreviation
Size
Supported
Access Sizes
WIREER
32
32
WIFEER
32
32
WIFER
32
32
WIPUER
32
32
NOTE
Reserved registers will read as 0, writes will have no effect. If supported and
enabled by the SoC, a transfer error will be issued when trying to access
completely reserved register space.
41.4.2 Register Description
This section describes in address order all the Wakeup Unit registers. Each description includes a standard
register diagram with an associated figure number. Details of register bit and field function follow the
register diagrams, in bit order. The numbering convention of register is MSB=0, however the numering of
internal field is LSB=0, e.g. EIF[5] = WISR[26].
Always 1 Always 0 R/W BIT Read- BIT Write-o
Write 1 BIT Self-clear 0 N/A
reads 1
reads 0
bit
only bit
nly bit
to clear
BIT
w1c
bit
BIT
Figure 41-2. Key to Register Fields
41.4.2.1 NMI Status Flag Register (NSR)
This register holds the non-maskable interrupt status flags.
Address:0x0000
0
1
2
3
4
5
6
7
8
R _{NIF NOVF 0}
0
0
0
0
0
0
W _{w1c w1c}
Reset ₀
0
0
0
0
0
0
0
0
Access: User read/write (write 1 to clear)
9
10 11 12 13 14 15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26 27 28 29 30 31
R₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 41-3. NMI Status Flag Register (NSR)
41-4
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor