PXD10RM Datasheet, PDF (784/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

assigned a priority according to the time from the request for the ISR to the deadline, not from the time of
the request for the ISR to the next request for it.
For example, ISR1 executes every 100 s, ISR2 executes every 200 s, and ISR3 executes every 300 s.
ISR1 has a higher priority than ISR2 which has a higher priority than ISR3; however, if ISR3 has a
deadline of 150 s, then it has a higher priority than ISR2.
The INTC has 16 priorities, which may be less than the number of ISRs. In this case, the ISRs should be
grouped with other ISRs that have similar deadlines. For example, a priority could be allocated for every
time the request rate doubles. ISRs with request rates around 1 ms would share a priority, ISRs with request
rates around 500 s would share a priority, ISRs with request rates around 250 s would share a priority,
etc. With this approach, a range of ISR request rates of 2¹⁶ could be included, regardless of the number of
ISRs.
Reducing the number of priorities reduces the processor’s ability to meet its deadlines. However, reducing
the number of priorities can reduce the size and latency through the interrupt controller. It also allows
easier management of ISRs with similar deadlines that share a resource. They do not need to use the PCP
to access the shared resource.
21.7.7 Software configurable interrupt requests
The software configurable interrupt requests can be used in two ways. They can be used to schedule a
lower priority portion of an ISR and they may also be used by processors to interrupt other processors in
a multiple processor system.
21.7.7.1 Scheduling a lower priority portion of an ISR
A portion of an ISR needs to be executed at the PRIx value in INTC_PSR0_3 -INTC_PSR204_206, which
becomes the PRI value in INTC_CPR with the interrupt acknowledge. The ISR, however, can have a
portion that does not need to be executed at this higher priority. Therefore, executing the later portion that
does not need to be executed at this higher priority can prevent the execution of ISRs which do not have a
higher priority than the earlier portion of the ISR but do have a higher priority than what the later portion
of the ISR needs. This preemptive scheduling inefficiency reduces the processor’s ability to meet its
deadlines.
One option is for the ISR to complete the earlier higher priority portion, but then schedule through the
RTOS a task to execute the later lower priority portion. However, some RTOSs can require a large amount
of time for an ISR to schedule a task. Therefore, a second option is for the ISR, after completing the higher
priority portion, to set a SETx bit in INTC_SSCIR0_3–INTC_SSCIR4_7. Writing a 1 to SETx causes a
software configurable interrupt request. This software configurable interrupt request will usually have a
lower PRIx value in the INTC_PSRx_x and will not cause preemptive scheduling inefficiencies. After
generating a software settable interrupt request, the higher priority ISR completes. The lower priority ISR
is scheduled according to its priority. Execution of the higher priority ISR is not resumed after the
completion of the lower priority ISR.
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PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor