PXD10RM Datasheet, PDF (1205/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

37.5.3.7 Interrupt Filter Enable Register (IFER)
This register is used to enable a digital filter counter on the corresponding external interrupt pads to filter
out glitches on the inputs.
Address: Base + 0x0030
Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
IFE[13:0]¹
W
Reset _{0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0}
Figure 37-9. Interrupt Filter Enable Register (IFER)
1 _{IFE[11:0] is valid in the 144-pin LQFP.}
Field
IFE[x]
Table 37-9. IFER Field Descriptions
Description
Enable digital glitch filter on the interrupt pad input.
1: Filter is enabled
0: Filter is disabled
37.5.3.8 Pad Configuration Registers (PCR0 - PCR132)
The Pad Configuration Registers allow configuration of the static electrical and functional characteristics
associated with I/O pads. Each PCR controls the characteristics of a single pad.
Address: Base + 0x0040 (PCR0)(133 registers)
Base + 0x0042 (PCR1)
...
Base + 0x0148 (PCR132)
0
1
2
3
R
SMC APC
W
Reset¹ ₀
0
0
0
4
5
6
7
8
PA[1:0] OBE IBE
0
0
0
0
0
Access: User read/write
9
10
11
12
13
14
15
ODE
SRC[1:0] WPE WPS
0
0
0
0
0
0
0
1 _{Reset value shown is for the most of the PCRs, however, some PCRs are initialized to different values dependent}
on the requirements of the device. See Chapter 3, Signal Description,” for the reset configurations of each PCR on
this device.
Figure 37-10. Pad Configuration Registers (PCRx)
NOTE
16/32-bit access supported
In addition to the bit map above, the following Table 37-11 describes the PCR register depending on the
pad type. The bits in shaded fields are not implemented for the particular I/O type. The PA field selecting
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
37-11