PXD10RM Datasheet, PDF (1192/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Setting the BLNDIV or ITGDIV bits will influence the resolution of the down counter in the
corresponding phase of the BIS (fine resolution required for blanking) as well as the available (absolute)
time interval that can be covered by the length of the DCNT register (must be long enough to cover almost
one SM step movement for integration). Due to the different prescaler settings for blanking and integration
no compromise is necessary between fine resolution for blanking and long time for integration when using
high bus frequencies.
It is recommended to select the setting with the best timing resolution for the blanking phase for the
BLNDIV bit setting (lowest value). Most likely a different value must be chosen for the ITGDIV bit
setting, nevertheless the lowest possible value should be chosen, too.
Note that in normal operation it should not occur that the ACOVIF bit in the IRQ register reads out to be
set during the integration. If this happens the bit indicates that either an overflow or an underflow occurred
in the ITGACC register. The result should be discarded because the setup of the SSD block was wrong for
the current SSD attempt.
36.6.2.2 Offset Cancellation Considerations
Note that the polarity switching for offset cancellation like depicted in Figure 36-11 is controlled by the
DCNT register update which is updated depending from the ITGDIV settings. All the divider settings are
powers of 2, so the distance in time between two DCNT register updates is always an integer multiple or
divider of the ITGACC register update, depending which divider factor is greater than the other one.
If the offset cancellation is used the measurement polarity in the analog block is reverted at least once
during the integration phase. As a consequence the -modulator needs some time after each polarity flip
to achieve a stable output. An estimation for that time is given in Section 36.5.2, Analog Block Polarity
Switching Time”.
If the ITGACC register is updated before the -modulator output is stable at least one count is incorrect.
Since the next polarity flip takes place in the opposite direction this incorrect count will be compensated
for by the following polarity flip. Therefore it may be useful to add a small number of DCNT register
updates to the integration phase to have an even number of polarity flips in the offset cancellation.
Another mean to improve accuracy is to adjust the DCNT register updates where the polarity switches
occur with respect to the following ITGACC register update to allow enough settling time for the
-modulator output.
36.6.3 Watching Internal States of the SSD
For some applications it might be required by the application to know the current state of an ongoing BIS.
It is recommended to do that by reading the BLNST and the ITGST bits of the CONTROL register. If
necessary the DCNT register value may be read to know how far the DCNT register period has expired.
Do not poll the DCNT register value for 0x0000 to find out the end of the blanking or integration phase.
Aside from generating more CPU load than required this introduces an inaccuracy. Not earlier than the
DCNT register divider period belonging to the 0x0000 value has expired the complete blanking or
integration phase has been processed.
36-26
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor