PXD10RM Datasheet, PDF (924/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

25.3.2.5 Interrupt Mask Register (ME_IM)
Address 0xC3FD_C010
Access: Supervisor read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R0
0
0
0
0
0
0
0
0
0
0
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 25-6. Interrupt Mask Register (ME_IM)
This register controls whether an event generates an interrupt or not.
Table 25-8. Interrupt Mask Register (ME_IM) Field Descriptions
Field
Description
M_ICONF
M_IMODE
M_SAFE
M_MTC
Invalid mode configuration interrupt mask
0 Invalid mode interrupt is masked
1 Invalid mode interrupt is enabled
Invalid mode interrupt mask
0 Invalid mode interrupt is masked
1 Invalid mode interrupt is enabled
SAFE mode interrupt mask
0 SAFE mode interrupt is masked
1 SAFE mode interrupt is enabled
Mode transition complete interrupt mask
0 Mode transition complete interrupt is masked
1 Mode transition complete interrupt is enabled
25-18
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor