PXD10RM Datasheet, PDF (248/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Table 9-17. UC Input Filter Bits
IF[0:3]¹
Minimum input Pulse width [FLT_CLK periods]
0000
bypassed²
0001
02
0010
04
0100
08
1000
16
all others
reserved
1 _{Filter latency is 3 clock edges.}
2 _{The input signal is synchronized before arriving to the digital filter.}
BSL[0:1]
00
01
10
11
Table 9-18. UC BSL bits
selected bus
All channels: counter bus[A]
Channels 8 to 15: counter bus[C]
Channels 16 to 23: counter bus[D]
reserved
All channels: internal counter
9-22
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor