PXD10RM Datasheet, PDF (1157/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

PWM duty cycle value MCDCx[DUTY]. When a match (output compare between motor controller timer
counter and MCDCx[DUTY]) occurs, the PWM output will toggle to a logic high level and will remain at
a logic high level until the motor controller timer counter overflows (reaches the value defined by
MCPER[PER[10:1]] – 1). After the motor controller timer counter resets to 0x000, the PWM output will
return to a logic low level. This completes the first half of the PWM period. During the second half of the
PWM period, the PWM output will remain at a logic low level until either the motor controller timer
counter matches the 10-bit PWM duty cycle value MCDCx[DUTY] if MCDCx[DUTY[0]]= 0, or the
motor controller timer counter matches the 10-bit PWM duty cycle value + 1 (the value of
MCDCx[DUTY[10:1]] is incremented by 1 and is compared with the motor controller timer counter value)
if MCDCx[DUTY[0]] = 1 for the corresponding channel. When a match occurs, the PWM output will
toggle to a logic high level and will remain at a logic high level until the motor controller timer counter
overflows (reaches the value defined by MCPER[PER[10:1]] – 1). After the motor controller timer counter
resets to 0x000, the PWM output will return to a logic low level.
This process will repeat every number of counts of the motor controller timer counter defined by the period
register contents (MCPER[PER]). If the output is neither set to 0% nor to 100% there will be four edges
on the PWM output per PWM period in this case. Therefore, the PWM output compare function will
alternate between MCDCx[DUTY] and MCDCx[DUTY] + 1 every half PWM period if
MCDCx[DUTY[0]] for the corresponding channel is set to 1. The relationship between the motor
controller timer counter clock (f_TC), motor controller timer counter value, and left aligned PWM output if
MCCTL0[DITH] = 1 is shown in Figure 35-28 and Figure 35-29. Figure 35-30 and Figure 35-31 show
right aligned and center aligned PWM operation respectively, with dither feature enabled and
MCDCx[DUTY[0]] = 1. Please note: In the following examples, the MCPER[PER] value, which is, if
MCCTL0[DITH] = 1, always an even number.
NOTE
The MCCTL0[DITH] bit must be changed only if the SMC is disabled (all
channels disabled or period register cleared) to avoid erroneous waveforms.
Motor Controller
Timer Counter
Clock
Motor Controller
Timer Counter
0
15
16
99 0
15
16
99 0
PWM Output
100 Counts
1 Period
100 Counts
Figure 35-28. PWM Output: MCCTL0[DITH] = 1, MCCCx[MCAM] = 0x1, MCDCx[DUTY] = 31, MCPER[PER] =
200, MCCTL1[RECIRC] = 0
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
35-29