PXD10RM Datasheet, PDF (493/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Register address: DMA_Offset + 0x0020 (DMAINTH), +0x0024 (DMAINTL)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R INT6 INT6 INT6 INT6 INT5 INT5 INT5 INT5 INT5 INT5 INT5 INT5 INT5 INT5 INT4 INT4
W
3210987654321098
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R INT4 INT4 INT4 INT4 INT4 INT4 INT4 INT4 INT3 INT3 INT3 INT3 INT3 INT3 INT3 INT3
W
7654321098765432
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R INT3 INT3 INT2 INT2 INT2 INT2 INT2 INT2 INT2 INT2 INT2 INT2 INT1 INT1 INT1 INT1
W
1098765432109876
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R INT1 INT1 INT1 INT1 INT1 INT1 INT0 INT0 INT0 INT0 INT0 INT0 INT0 INT0 INT0 INT0
W
5432109876543210
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
= Unimplemented
Figure 15-14. DMA Interrupt Request (DMAINTH, DMAINTL) Registers
Table 15-14. DMA Interrupt Request (DMAINTH, DMAINTL) field descriptions
Name
INTn,
n = 0,... 15
n = 0,... 31
n = 0,... 63
Description
DMA Interrupt Request n
Value
0 The interrupt request for channel n is cleared.
1 The interrupt request for channel n is active.
15.2.1.14 DMA Error (DMAERRH, DMAERRL)
The DMAERR{H,L} registers provide a bit map for the implemented channels {16,32,64} signaling the
presence of an error for each channel. DMAERRH supports channels 63-32, while DMAERRL covers
channels 31-00. The DMA engine signals the occurrence of a error condition by setting the appropriate bit
in this register. The outputs of this register are enabled by the contents of the DMAEEI register, then
logically summed across groups of 16, 32 and 64 channels to form several group error interrupt requests
which is then routed to the platform’s interrupt controller. During the execution of the interrupt service
routine associated with any DMA errors, it is software’s responsibility to clear the appropriate bit, negating
the error interrupt request. Typically, a write to the DMACERR register in the interrupt service routine is
used for this purpose. Recall the normal DMA channel completion indicators, setting the transfer control
descriptor done flag and the possible assertion of an interrupt request, are not affected when an error is
detected.
The contents of this register can also be polled and a non-zero value indicates the presence of a channel
error, regardless of the state of the DMAEEI register. The state of any given channel’s error indicators is
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
15-23