PXD10RM Datasheet, PDF (699/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

on a per Message Buffer basis. When the FIFO is enabled (FEN bit in MCR is set), the first 8 Mask
Registers apply to the 8 elements of the FIFO filter table (on a one-to-one correspondence), while the rest
of the registers apply to the regular MBs, starting from MB8.
The Individual Rx Mask Registers are implemented in RAM, so they are not affected by reset and must be
explicitly initialized prior to any reception. Furthermore, they can only be accessed by the CPU while the
module is in Freeze Mode. Out of Freeze Mode, write accesses are blocked and read accesses will return
“all zeros”. Furthermore, if the BCC bit in the MCR Register is negated, any read or write operation to
these registers results in access error.
Base + 0x0004
0
R _MI31
W
1
MI30
2
MI29
3
MI28
4
MI27
5
MI26
6
MI25
7
MI24
8
MI23
9
MI22
10
MI21
11
MI20
12
MI19
13
MI18
14
MI17
15
MI16
RESET: ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R _{MI15 MI14 MI13 MI12 MI11 MI10 MI9 MI8 MI7 MI6 MI5 MI4 MI3 MI2 MI1 MI0}
W
RESET: ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 18-15. Rx Individual Mask Registers (RXIMR0 - RXIMR63)
Table 18-18. Rx Individual Mask Registers (RXIMR0 - RXIMR63) Field Descriptions
Field
0-31
MI31–MI0
Description
Mask Bits
For normal Rx MBs, the mask bits affect the ID filter programmed on the MB. For the Rx FIFO, the
mask bits affect all bits programmed in the filter table (ID, IDE, RTR).
1 = The corresponding bit in the filter is checked against the one received
0 = the corresponding bit in the filter is “don’t care”
18.4 Functional description
18.4.1 Overview
The FlexCAN module is a CAN protocol engine with a very flexible mailbox system for transmitting and
receiving CAN frames. The mailbox system is composed by a set of up to 64 Message Buffers (MB) that
store configuration and control data, time stamp, message ID and data (see Section 18.3.2, Message Buffer
Structure). The memory corresponding to the first 8 MBs can be configured to support a FIFO reception
scheme with a powerful ID filtering mechanism, capable of checking incoming frames against a table of
IDs (up to 8 extended IDs or 16 standard IDs or 32 8-bit ID slices), each one with its own individual mask
register. Simultaneous reception through FIFO and mailbox is supported. For mailbox reception, a
matching algorithm makes it possible to store received frames only into MBs that have the same ID
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
18-29