PXD10RM Datasheet, PDF (482/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Name
EMLM
CLM
HALT
HOE
ERGA
ERCA
EDBG
EBW
Table 15-2. DMA Control Register (DMACR) field descriptions
Description
Value
Enable Minor Loop Mapping
0 Minor loop mapping disabled. TCDn.word2 is
defined as a 32-bit nbytes field.
1 Minor loop mapping enabled. When set,
TCDn.word2 is redefined to include individual
enable fields, an offset field and the nbytes field. The
individual enable fields allow the minor loop offset to
be applied to the source address, the destination
address, or both. The nbytes field is reduced when
either offset is enabled.
Continuous Link Mode
0 A minor loop channel link made to itself will go
through channel arbitration before being activated
again.
1 A minor loop channel link made to itself will not go
through channel arbitration before being activated
again. Upon minor loop completion the channel will
active again if that channel has has a minor loop
channel link enabled and the link channel is itself.
This effectively applies the minor loop offsets and
restarts the next minor loop.
Halt DMA Operations
0 Normal operation.
1 Stall the start of any new channels. Executing
channels are allowed to complete. Channel
execution will resume when the HALT bit is cleared.
Halt On Error
0 Normal operation.
1 Any error will cause the HALT bit to be set.
Subsequently, all service requests will be ignored
until the HALT bit is cleared.
Enable Round Robin Group Arbitration
0 Fixed priority arbitration is used for selection among
the groups.
1 Round robin arbitration is used for selection among
the groups.
Enable Round Robin Channel Arbitration
0 Fixed priority arbitration is used for channel
selection within each group.
1 Round robin arbitration is used for channel selection
within each group.
Enable Debug
0 The assertion of the ipg_debug input is ignored.
1 The assertion of the ipg_debug input causes the
DMA to stall the start of a new channel. Executing
channels are allowed to complete. Channel
execution will resume when either the ipg_debug
input is negated or the EDBG bit is cleared.
Enable Buffered Writes
0 The bufferable write signal (hprot[2]) is not asserted
during AMBA AHB writes.
1 The bufferable write signal (hprot[2]) is asserted on
all AMBA AHB writes except for the last write
sequence.
15-12
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor