PXD10RM Datasheet, PDF (1056/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

SCK (CPOL = 0)
SCK (CPOL = 1)
Master SO
Master SI
PCSx
t_CSC
t_ASC t_{DT tCSC}
t_CSC = PCS to SCK delay
t_ASC = After SCK delay
t_DT = Delay after Transfer (minimum CS negation time)
Figure 30-31. Example of Non-Continuous Format (CPHA=1, CONT=0)
When the CONT bit = 1, the PCS signal remains asserted for the duration of the two transfers. The Delay
between Transfers (t_DT) is not inserted between the transfers. Figure 30-32 shows the timing diagram for
two four-bit transfers with CPHA = 1 and CONT = 1.
SCK (CPOL = 0)
SCK (CPOL = 1)
Master SO
Master SI
PCS
t_CSC
t_CSC = PCS to SCK delay
t_ASC = After SCK delay
t_ASC t_CSC
Figure 30-32. Example of Continuous Transfer (CPHA=1, CONT=1)
Switching CTAR registers or changing which PCS signals are asserted between frames while using
Continuous Selection can cause errors in the transfer. The PCS signal should be negated before CTAR is
switched or different PCS signals are selected.
30-52
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor